1. Field of the Invention
The present invention relates to a dynamic type random-access memory having a charge transfer circuit between a bit line pair and a bit line sense amplifier.
2. Description of the Related Art
In a conventional large-capacity dynamic random-access memory (to be referred to as a DRAM hereinafter), as shown in FIG. 1, charge transfer transistors NT.sub.1 and NT.sub.2 comprising insulating gate type field effect transistors (MOS transistors) are connected between a pair of bit lines BL and BL and a bit line sense amplifier NA of each column so that the bit line sense amplifier can rapidly sense-amplify a potential difference produced in the bit line pair upon reading out of memory cell data.
That is, referring to FIG. 1, reference symbols BL and BL denote first and second bit lines constituting a bit line pair of each column in a memory cell array of the DRAM; MC.sub.i (i=0 to 255), a plurality of dynamic memory cells connected to each of the bit lines BL and BL; DC.sub.0 and DC.sub.1, dummy cells connected to the first and second bit lines BL and BL, respectively; WL.sub.i (i=0 to 255), a word line connected to the gate of a charge transfer transistor TM of the memory cell MC.sub.i ; DWL.sub.0 and DWL.sub.1, dummy word lines connected to the gates of charge transfer transistors TD of the dummy cells DC.sub.0 and DC.sub.1, respectively; and TW.sub.0 and TW.sub.1, dummy cell write transistors for writing dummy cell write voltage V.sub.DC in the dummy cells DC.sub.0 and DC.sub.1, respectively. The transistors TW.sub.0 and TW.sub.1 are enabled by an equalize signal EQL. Reference symbol PR denotes a precharge/equalize circuit for precharging and equalizing the bit lines BL and BL to a precharge voltage V.sub.BL (set to be, e.g., 1/2 a power source voltage V.sub.CC). The circuit PR is enabled by an equalize signal EQL (bit line precharge dummy cell write signal). Reference symbol PA denotes a bit line restore p-channel sense amplifier in which the drains of two p-channel transistors P.sub.1 and P.sub.2 having cross-connected gates and drains are connected to the bit lines BL and BL, respectively, and which is enabled by a p-channel sense amplifier enable signal SAP; and NA, an n-channel sense amplifier in which the drains (a pair of sense nodes SN and SN) of two n-channel transistors N.sub.1 and N.sub.2 having cross-connected gates and drains are connected to the other terminals of the charge transfer transistors NT.sub.1 and NT.sub.2, respectively, and which is enabled by an n-channel sense amplifier enable signal SAN.
The charge transfer transistors NT.sub.1 and NT.sub.2 are so controlled as to be kept OFF for a predetermined time period immediately before the n-channel sense amplifier NA is enabled when the gates of the transistors NT.sub.1 and NT.sub.2 receive a drive signal .phi..sub.T from a charge transfer transistor driver (not shown).
The pair of sense nodes SN and SN of the n-channel sense amplifier NA are connected to a pair of column selection transistors CT.sub.1 and CT.sub.2, respectively. The pair of column selection transistors CT.sub.1 and CT.sub.2 are connected to a pair of data buses DL.sub.1 and DL.sub.2 via a pair of data lines DQ.sub.1 and DQ.sub.2 connected in common to a plurality of columns, respectively, and a data buffer DQB.
A conventional operation of the DRAM having the above arrangement will be described below with reference to waveforms shown in FIG. 2. Assuming that data indicating a potential of 0 V ("L" level) is written in a memory cell MC.sub.1 connected to one bit line of the bit line pair, e.g., the bit line BL, read and rewrite operations performed for the memory cell MC.sub.1 will be described.
Since this DRAM has a V.sub.CC potential of, e.g., 5 V and adopts a driving system for precharging the bit line pair to a voltage of V.sub.BL =V.sub.CC /2, the first and second bit lines BL and BL are equally kept at V.sub.CC /2 before a word line is selected. Row and column addresses are sequentially input as address inputs, and a row address strobe signal RAS is enabled after the row address is input, thereby decoding the row address. A word line WL.sub.1 at the bit line BL side is selected to turn on the charge transfer transistor TM of the selected memory cell MC.sub.1, and the data of 0 V ("L" level) is read out from a capacitor C.sub.1 of the memory cell MC.sub.1. Therefore, a potential of the first bit line BL is slightly reduced from V.sub.CC /2.
At the same time the word line WL.sub.1 at the first bit line BL side is selected, the dummy word line DWL.sub.0 at the second bit line BL side is selected to turn on the charge transfer transistor TD of the dummy cell DC.sub.0. In this case, a potential of V.sub.DC (e.g., V.sub.CC /2) is prewritten in the dummy cell DC.sub.0. Therefore, even if the charge transfer transistor TD is turned on to short-circuit a capacitor C.sub.0 and the second bit line BL, a potential of the second bit line BL is kept at V.sub.CC /2 because the capacitor C.sub.0 and the second bit line BL are at the same potential.
Thereafter, when a small potential difference is produced between the potentials of the first and second bit lines BL and BL, the signal .phi.T goes to a potential V.sub.SS, the charge transfer transistors NT.sub.1 and NT.sub.2 are turned off, and the bit lines BL and BL are disconnected from the bit line sense amplifier NA. A signal SAN goes to the ground potential V.sub.SS to enable the n-channel sense amplifier NA, and a signal SAP goes to the potential V.sub.CC to enable the p-channel sense amplifier PA. As a result, a small potential difference between the pair of sense nodes SN and SN of the sense amplifier NA is sense-amplified, and a potential of the sense node SN is reduced to 0 V.
In addition, the potential of the bit line BL is increased to the potential V.sub.CC side by the p-channel sense amplifier PA. Thereafter, a column address strobe signal CAS is enabled to decode the column address, and the pair of column selection transistors CT.sub.1 and CT.sub.2 are turned on by a column decode signal CSL.sub.i. When the transistors CT.sub.1 and CT.sub.2 are turned on, the potentials of the sense nodes SN and SN of the sense amplifier NA are reamplified by the data buffer DQB and output to the pair of data buses DL.sub.1 and DL.sub.2 via the pair of data lines DQ.sub.1 and DQ.sub.2, respectively. When the signal .phi..sub.T returns to the potential V.sub.CC to turn on the charge transfer transistors NT.sub.1 and NT.sub.2, the bit lines BL and BL are connected to the sense nodes SN and SN of the bit line sense amplifier NA. The potential of the first bit line BL is reduced to 0 V, and that of the second sense node SN is increased to the potential V.sub.CC (e.g., 5 V). Therefore, data of "L" level and that of "H" level are rewritten in the selection memory cell MC.sub.1 and the dummy cell DC.sub.0, respectively. Thereafter, the word line WL.sub.1 and the dummy word line DWL.sub.0 return to a nonselection state.
After the above rewrite operation is completed, the bit line precharge dummy cell write signal EQL goes to the potential V.sub.CC, the bit line BL and BL are precharged to the voltage V.sub.BL, and the dummy cells DC.sub.0 and DC.sub.1 are precharged to the voltage V.sub.DC.
In the above DRAM, since the capacitances of the bit lines BL and BL are completely disconnected from the pair of sense nodes SN and SN during an operation of the sense amplifier NA, loads on the sense nodes SN and SN are reduced to increase a speed of sense amplification. Therefore, an access time t.sub.ACC from a fall timing of the signal RAS to an output timing of readout data can be shortened.
In the above operation of the DRAM, however, when the charge transfer transistors NT.sub.1 and NT.sub.2 return from an OFF to ON state, a large amount of charges simultaneously flow from the first bit line BL to be reduced to the "L" level side to the sense node SN of the sense amplifier NA, and the potential of the sense node SN is abruptly increased. In this state, a current driving power of the sense amplifier NA is reduced. Therefore, if the column selection transistors CT.sub.1 and CT.sub.2 are turned on in this state, a speed of extracting charges from the data line DQ.sub.1 (precharged to, e.g., the potential V.sub.CC) connected to the sense node SN may be decreased to disable reamplification in the data buffer DQB.
That is, if a time t.sub.RAD from an enable timing (in this case, a fall timing) of the signal RAS to an input timing of a column address is shorter or longer than a predetermined range, the potential of the sense node SN of the sense amplifier NA has almost no increase when the column selection transistors CT.sub.1 and CT.sub.2 are turned on after the column address is input. Therefore, reamplification can be correctly performed in the data buffer DQB.
If, however, the time t.sub.RAD from the enable timing of the signal RAS to the input timing of the column address falls within the predetermined range, the potential of the sense node SN of the sense amplifier is increased as described above when the column selection transistors CT.sub.1 and CT.sub.2 are turned on after the column address is input. Therefore, reamplification cannot be correctly performed in the data buffer DQB to cause a read error.
In the DRAM having the above arrangement, therefore, a read error is caused when the time t.sub.RAD from the enable timing of the signal RAS to the input timing of the column address falls within a predetermined range.